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| renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 1 / 25 m5m5v5636ug - 16 rev.2.0 description the m5m5v5636ug is a family of 18m bit synchronous srams organized as 524288 - words by 36 - bit. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. renesas's srams are fabricated with high performance, low power cmos technology, providing greater reliability. m5m5v5636ug operates on 3.3v power/ 2.5v i/o supply or a single 3.3v power supply and are 3.3v cmos compatible. the m5m5v5636ug also operates on a single 2.5v power supply and is also 2.5v cmos compatible. therefore the m5m5v5636ug can replace the m5m5t5636ug. the m5m5v5636ug - 16 operates at 167mhz or 133mhz and is guaranteed both ac dc electrical characteristics of 167mhz and those of 133mhz. features ? fully registered inputs and outputs for pipelined operation ? fast clock speed: 167 and 133 mhz ? fast access time: 3.8 and 4.2 ns ? single 3.3v - 5% and +5% power supply v dd ? separate v ddq for 3.3v or 2.5v i/o ? single 2.5v - 5% and +5% power supply v dd ? individual byte write ( bwa# - bwd#) controls may be tied low ? single read/write control pin (w#) ? cke# pin to enable clock and suspend operations ? internally self - timed, registers outputs eliminate the need to control g# ? snooze mode ( zz) for power down ? linear or interleav ed burst modes ? three chip enables for simple depth expansion ? jtag boundary scan support package 165(11x15) bump bga body size (13mm x 15mm) bump pitch 1.0mm application high - end networking products that require high bandwidth, such as switches an d routers . function synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. synchronous signals include : all addresses, all data inputs, all chip enables (e1# , e2, e3#), address advance/load (adv), clock ena ble (cke#), byte write enables (bwa# , bwb#, bwc#, bwd# ) and read/write (w#). write operations are controlled by the four byte write enables (bwa# - bwd#) and read/write(w#) inputs. all writes are conducted with on - chip synchronous self - timed write circuitr y. asynchronous inputs include output enable (g# ), clock ( clk) and snooze enable ( zz) . the high input of zz pin puts the sram in the power - down state.the linear burst order ( lbo#) is dc operated pin. lbo# pin will allow the choice of either an interleaved burst, or a linear burst. all read, write and deselect cycles are initiated by the adv low input. subsequent burst address can be internally generated as controlled by the adv high input. part name table m5m5v5636ug - 16 operate frequency access cycle active current (max.) standby current (max.) 167mhz 3.8ns 6.0ns 380ma 30ma 133mhz 4.2ns 7.5ns 350ma 30ma
renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 2 / 25 m5m5v5636ug - 16 rev.2.0 bump layout(top view) 165bump - bga 1 2 3 4 5 6 7 8 9 10 11 a nc a 7 e1# bwc# bwb# e3# cke# adv a 17 a 8 nc b nc a 6 e2 b wd# bwa# clk w# g# a 18 a 9 nc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h mch mch nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc nc mch v ss v ddq nc dqpa p nc nc a 5 a 3 tdi a1 tdo a 15 a 13 a 11 nc r lbo# nc a 4 a 2 tms a0 tck a 16 a 14 a 12 a 10 note1. mch means "must connect high". mch should be connected to high. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 3 / 25 m5m5v5636ug - 16 rev.2.0 block diagram note2. the block diagram does not include the boundary scan logic. see boundary scan chapter. note3. the block diagram illustrates simplified device operation. see truth table, pin function and timing diagrams for detailed information. address register 19 write address register1 write address register2 a1 a0 linear/ interleaved burst counter d1 d0 q1 q0 a1' a0' 19 17 write registry and data coherency control logic byte1 write drivers byte2 wr ite drivers byte3 write drivers byte4 write drivers 256kx36 memory array output registers output select output buffers input register1 input register0 read logic 19 19 36 dqa lbo# dqpa dqb dqpb dqc dqpc dqd dqpd a0 a1 a2 ~ 18 clk cke# zz e2 e1# e3# g# bwa# bwb# bwc# bwd# adv w# v dd v ddq v ss renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 4 / 25 m5m5v5636ug - 16 rev.2.0 pin function pin name function a0 ~ a18 syn chronous address inputs these inputs are registered and must meet the setup and hold times around the rising edge of clk. a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bwa#, bwb#, bwc#, bwd# synchronous byte write enables these active low inputs allow individual bytes to be written when a write cycle is active and must meet the setup and hold times around the rising edge of clk. byte writes need to be asserted on the same cyc le as the address. bws are associated with addresses and apply to subsequent data. bwa# controls dqa, dqpa pins; bwb# controls dqb, dqpb pins; bwc# controls dqc, dqpc pins; bwd# controls dqd, dqpd pins. clk clock input this signal registers the address, d ata, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock's rising edge. e1# synchronous chip enable this active low input is used to enable the device and i s sampled only when a new external address is loaded (adv is low). e2 synchronous chip enable this active high input is used to enable the device and is sampled only when a new external address is loaded (adv is low). this input can be used for memory de pth expansion. e3# synchronous chip enable this active low input is used to enable the device and is sampled only when a new external address is loaded (adv is low). this input can be used for memory depth expansion. g# output enable this active low asyn chronous input enable the data i/o output drivers. adv synchronous address advance/load when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when high, w# is ignored. a low on this pin permits a new address to be loaded at clk rising edge. cke# synchronous clock enable this active low input permits clk to propagate throughout the device. when high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. zz snooze enable this active high asynchronous input causes the device to enter a low - power standby mode in which all data in the memory array is retained. when active, a ll other inputs are ignored. when this pin is low or nc, the sram normally operates. w# synchronous read/write this active input determines the cycle type when adv is low. this is the only means for determining reads and writes. read cycles may not be con verted into writes (and vice versa) other than by loading a new address. a low on the pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus width writes occur if all byte write enables are low. dq a,dqpa,dqb,dqpb dqc,dqpc,dqd,dqpd synchronous data i/o byte ? a ? is dqa , dqpa pins; byte ? b ? is dqb, dqpb pins; byte ? c ? is dqc, dqpc pins; byte ? d ? is dqd,dqpd pins. input data must meet setup and hold times around clk rising edge. lbo# burst mode contro l this dc operated pin allows the choice of either an interleaved burst or a linear burst. if this pin is high or nc, an interleaved burst occurs. when this pin is low, a linear burst occurs, and input leak current to this pin. v dd v dd core power supply v ss v ss ground v ddq v ddq i/o buffer power supply tdi test data input tdo test data output tck test clock tms test mode select these pins are used for boundary scan test. mch must connect high these pins should be connected to high nc no connect t hese pins are not internally connected and may be connected to ground. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 5 / 25 m5m5v5636ug - 16 rev.2.0 dc operated truth table name input status operation high or nc interleaved burst sequence lbo# low linear burst sequence note4. lbo# is dc operated pin. note5. nc means no connec tion. note6. see burst sequence table about interleaved and linear burst sequence. burst sequence table interleaved burst sequence (when lbo# = high or nc) operation a18 ~ a2 a1,a0 first access, latch external address a18 ~ a2 0 , 0 0 , 1 1 , 0 1 , 1 second access(first burst address) latched a18 ~ a2 0 , 1 0 , 0 1 , 1 1 , 0 third access(second burst address) latched a18 ~ a2 1 , 0 1 , 1 0 , 0 0 , 1 fourth access(third burst address) latched a18 ~ a2 1 , 1 1 , 0 0 , 1 0 , 0 linear burst sequence (when lbo# = lo w) operation a18 ~ a2 a1,a0 first access, latch external address a18 ~ a2 0 , 0 0 , 1 1 , 0 1 , 1 second access(first burst address) latched a18 ~ a2 0 , 1 1 , 0 1 , 1 0 , 0 third access(second burst address) latched a18 ~ a2 1 , 0 1 , 1 0 , 0 0 , 1 fourth acc ess(third burst address) latched a18 ~ a2 1 , 1 0 , 0 0 , 1 1 , 0 note7. the burst sequence wraps around to its initial state upon completion. truth table e1# e2 e3# zz adv w# bwx# g# cke# clk dq address used operation h x x l l x x x l l - >h high - z none d eselect cycle x l x l l x x x l l - >h high - z none deselect cycle x x h l l x x x l l - >h high - z none deselect cycle x x x l h x x x l l - >h high - z none continue deselect cycle l h l l l h x l l l - >h q external read cycle, begin burst x x x l h x x l l l - >h q next read cycle, continue burst l h l l l h x h l l - >h high - z external nop/dummy read, begin burst x x x l h x x h l l - >h high - z next dummy read, continue burst l h l l l l l x l l - >h d external write cycle, begin burst x x x l h x l x l l - >h d ne xt write cycle, continue burst l h l l l l h x l l - >h high - z none nop/write abort, begin burst x x x l h x h x l l - >h high - z next write abort, continue burst x x x l x x x x h l - >h - current ignore clock edge, stall x x x h x x x x x x high - z none snoo ze mode note8. ? h ? = input vih; ? l ? = input vil; ? x ? = input vih or vil. note9. bwx#=h means all synchronous byte write enables (bwa#,bwb#,bwc#,bwd#) are high. bwx#=l means one or more synchronous byte write enables are low. note10. all inputs except g# a nd zz must meet setup and hold times around the rising edge (low to high) of clk. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 6 / 25 m5m5v5636ug - 16 rev.2.0 state diagram note11. the notation "x , x , x" controlling the state transitions above indicate the state of inputs e, adv and w# respectively. note12. if (e1# = l and e2 = h and e3# = l) then e="t" else e="f". note13. ? h ? = input vih; ? l ? = input vil; ? x ? = input vih or vil; ? t ? = input ? true ? ; ? f ? = input ? false ? . read begin burst t , l , h read continue burst write begin burst write continue burst deselect x , h , x x , h , x x , h , x t , l , l t , l , l t , l , h x , h , x t , l , h t , l , l x , h , x f , l , x t , l , h f , l , x f , l , x t , l , l t , l , l t , l , h transition next state curre nt state input command code f key renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 7 / 25 m5m5v5636ug - 16 rev.2.0 write truth table w# bwa# bwb# bwc# bwd# function h x x x x re ad l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d l l l l l write all bytes l h h h h write abort/nop note14. ? h ? =input vih; ? l ? =input vil; ? x ? =input vih or vil. note15. all inputs except g# and zz must m eet setup and hold times around the rising edge (low to high) of clk. absolute maximum ratings symbol parameter conditions ratings unit v dd power supply voltage - 1.0* ~ 4.6 v v ddq i/o buffer power supply voltage - 1.0* ~ 4.6 v v i input voltage - 1.0 ~ v ddq +1.0** v v o output voltage with respect to v ss - 1.0 ~ v ddq +1.0** v pd maximum power dissipation (v dd ) 1.6 w t opr operating temperature 0 ~ 70 c t stg(bias) storage temperature(bias) - 10 ~ 85 c t stg storage temperature - 55 ~ 125 c note16.* this is ? 1.0v when pulse width 2ns, and ? 0.5v in case of dc. ** this is ? 1.0v ~ v ddq +1.0v when pulse width 2ns, and ? 0.5v ~ v ddq +0.5v in case of dc. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 8 / 25 m5m5v5636ug - 16 rev.2.0 dc electrical characteristics1 (ta=0 ~ 70 c, v dd =3.135 ~ 3.465v, unless otherwise noted) limi ts symbol parameter condition min max unit v dd power supply voltage 3.135 3.465 v v ddq = 3.3v 3.135 3.465 v ddq i/o buffer power supply voltage v ddq = 2.5v 2.375 2.625 v v ddq = 3.135 ~ 3.465v 2.0 v ih high - level input voltage v ddq = 2.375 ~ 2.625v 1.7 v ddq +0.3* v v ddq = 3.135 ~ 3.465v 0.8 v il lo w - level input voltage v ddq = 2.375 ~ 2.625v - 0.3* 0.7 v v oh high - level output voltage i oh = - 2.0ma v ddq - 0.4 v v ol low - level output voltage i ol = 2.0ma 0.4 v input leakage current except zz and lbo# v i = 0v ~ v ddq 10 input leakage current of lbo# v i = 0v ~ v ddq 100 i li input leakage current of zz v i = 0v ~ v ddq 100 a i lo off - state output current v i (g#) 3 v ih , v o = 0v ~ v ddq 10 a 6.0ns cycle(167mhz) 380 i cc1 power supply current : operating device selected; output open v i v il or v i 3 v ih zz v il 7.5ns cycle(133mhz) 350 ma 6.0ns cycle(167mhz) 160 i cc2 power supply current : deselected device deselected v i v il or v i 3 v ih zz v il 7.5ns cycle(133mhz) 130 ma i cc3 cmos standby current (clk stopped standby mo de) device deselected; output open v i v ss +0.2v or v i 3 v ddq - 0.2v clk frequency=0hz, all inputs static 30 ma i cc4 snooze mode standby current snooze mode zz 3 v ddq - 0.2v, lbo# 3 v dd - 0.2v 30 ma 6.0ns cycle(167mhz) 130 i cc5 stall current device selected; output open cke# 3 v ih v i v ss +0.2 v or v i 3 v ddq - 0.2v 7.5ns cycle(133mhz) 120 ma note17.*v ilmin is ? 1.0v and v ih max is v ddq +1.0v in case of ac(pulse width 2ns). note18."device deselected" means device is in power - down mode as defined in the truth table. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 9 / 25 m5m5v5636ug - 16 rev.2.0 dc electrical characteristics 2 (ta=0 ~ 70 c, v dd =2.375 ~ 2.625v, unless otherwise noted) limits symbol parameter condition min max unit v dd power supply voltage 2.375 2.625 v v ddq i/o buffer power supply voltage 2.375 2.625 v v ih high - level input voltage 1.7 v ddq +0.3* v v il low - level input voltage - 0.3* 0.7 v v oh high - level output voltage i oh = - 2.0ma v ddq - 0.4 v v ol low - level output voltage i ol = 2.0ma 0.4 v input leakage current except zz and lbo# v i = 0v ~ v ddq 10 input leakage current of lbo# v i = 0v ~ v ddq 100 i li input leakage current of zz v i = 0v ~ v ddq 100 a i lo off - state output current v i (g#) 3 v ih , v o = 0v ~ v ddq 10 a 6.0ns cycle(167mhz) 380 i cc1 power supply current : operating device selected; output open, v i v il or v i 3 v ih, zz v il 7.5ns cycle(133mhz) 350 ma 6.0ns cycle(167mhz) 160 i cc2 power supply current : deselected device deselected v i v il or v i 3 v ih, zz v il 7.5ns cycle(133mhz) 130 ma i cc3 cmos standby current (clk stopped standby mode) device deselected; output open v i v ss +0.2v or v i 3 v ddq - 0.2v clk frequency=0hz, all inputs static 30 ma i cc4 snooze mode standby current snooze mode zz 3 v ddq - 0.2v, lbo# 3 v dd - 0.2v 30 ma 6.0ns cycle(167mhz) 130 i cc5 stall current device selected; output open, cke# 3 v ih v i v ss +0.2v or v i 3 v ddq - 0.2v 7.5ns cycle(133mhz) 120 ma note17.*v ilmin is ? 1.0v and v ih max is v ddq +1.0v in case of ac(pulse width 2ns). note18."device deselected" means device is in power - down mode as defined in the truth table. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 10 / 25 m5m5v5636ug - 16 rev.2.0 capacitance limits symbol parameter conditions min typ max unit c i input capacitance v i =gnd, v i =25mvrms, f=1mhz 6 pf c o input / output(dq) capacitance v o =gnd, v o =25mvrms, f=1mhz 8 pf note19.this parameter is sampled. thermal resistance 4 - layer pc board m ounted (70 x 70 x 1.6mmt) limits symbol parameter conditions min typ max unit q ja thermal resistance junction ambient air velocity=0m/sec 28 c/w air velocity=2m/sec 20 c/w q jc thermal resistance junction to case 4 c/w note20.this parameter is sampled. ac electrical characteristics ( ta=0 ~ 70 c, v dd =3.135 ~ 3.465v or v dd =2.375 ~ 2.625v, unless otherwise noted) (1)measurement condition input pulse levels v ih =v ddq , v il =0v input rise and fall times faster than or equal to 1v/ns input timing reference levels v ih =v il =0.5*v ddq output reference levels v ih =v il =0.5*v ddq output load fig.1 note21.valid delay measurement is made from the v ddq /2 on the input waveform to the v ddq /2 on the output waveform. input waveform should have a slew rate of faster than or equal to 1v/ns. note22.tri - s tate toff measurement is made from the v ddq /2 on the input waveform to the output waveform moving 20% from its initial to final value v ddq /2. note:the initial value is not v ol or v oh as specified in dc electrical characteristics table. note23. tri - state to n measurement is made from the v ddq /2 on the input waveform to the output waveform moving 20% from its initial value v ddq /2 to its final value. note:the final value is not v ol or v oh as specified in dc electrical characteristics table. note24.clock s,data,address and control signals will be tested with a minimum input slew rate of faster than or equal to 1v/ns. z o =50 w 50 w q v t =0.5*v ddq 30pf (including wiring and jig) fig.1 output load v ddq / 2 v ddq / 2 t plh t phl input waveform output waveform v ddq / 2 input waveform vh - (0.2(vh - vz)) vz+(0.2(vh - vz)) 0.2(vz - vl) vz - (0.2(vz - vl)) toff ton vz (toff) (ton) vh vl output waveform fig.2 tdly me asurement fig.3 tri - state measurement renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 11 / 25 m5m5v5636ug - 16 rev.2.0 (2)timing characteristics limits 167mhz 133mhz - 16 - 16 symbol parameter min max min max unit t khkh clock cycle time 6.0 7.5 ns t khkl clock high time 2.7 3.0 ns t klkh clock low time 2.7 3.0 ns t khqv clock high to output valid 3.8 4.2 ns t khqx clock high to output invalid 1.5 1.5 ns t khqx1 clock high to output in low - z 1.5 1.5 ns t khqz clock high to output in high - z 1.5 3.8 1.5 4.2 ns t glqv g# to output valid 3.8 4.2 ns t glqx1 g# to output in low - z 0.0 0.0 ns t ghqz g# to output in high - z 3.8 4.2 ns t avkh address valid to clock high 1.2 1.2 ns t c kevkh cke# valid to clock high 1.2 1.2 ns t advvkh adv valid to clock high 1.2 1.2 ns t wvkh write valid to clock high 1.2 1.2 ns t bvkh byte write valid to clock high (bwa# ~ bwd#) 1.2 1.2 ns t evkh enable valid to clock high (e1#,e2,e3#) 1.2 1.2 ns t dvkh data in valid clock high 1.2 1.2 ns t khax clock high to address don ? t care 0.8 0.8 ns t khckex clock high to cke# don ? t care 0.8 0.8 ns t khadvx clock high to adv don ? t care 0.8 0.8 ns t khwx clock high to wri te don ? t care 0.8 0.8 ns t khbx clock high to byte write don ? t care (bwa# ~ bwb#) 0.8 0.8 ns t khex clock high to enable don ? t care (e1#,e2,e3#) 0.8 0.8 ns t khdx clock high to data in don ? t care 0.8 0.8 ns t zzs zz standby 2*t kh kh 2*t khkh ns t zzrec zz recovery 2*t khkh 2*t khkh ns note25.all parameter except t zzs , t zzrec in this table are measured on condition that zz=low fix. note26.test conditions is specified with the output loading shown in fig.1 unless otherwise noted. note27. t khqx1 , t khqz , t glqx1 , t ghqz are sampled. note28.lbo# is static and must not change during normal operation. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 12 / 25 m5m5v5636ug - 16 rev.2.0 (3)read timing note 29.q(an) refers to output from address an. q(an+1) refers to output from the next internal burst address following an. note30. e# represents three signals. when e# is low, it represents e1# is low, e2 is high and e3# is low. note31.zz is fixed low . read a2 a1 a2 a3 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a3) q(a3+1) clk cke# e# adv w# bwx# add dq g# read a1 burst read a2+1 stall burst read a2+2 burst read a2+3 burst read a2 deselect continue deselect read a3 burst read a3+1 burst read a3+2 burst read a3+3 t khkh don't care undefined t klkh t khkl t khckex t ckevkh t khex t evkh t khadvx t advvkh t khwx t wvkh t khax t avkh t khqx1 t khqv t khqx t glqv t ghqz t glqx1 t khqz renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 13 / 25 m5m5v5636ug - 16 rev.2.0 (4)w rite timing note32.q(an) refers to output from address an. q(an+1) refers to output from the next i nternal burst address following an. note33. e# represents three signals. when e# is low, it represents e1# is low, e2 is high and e3# is low. note34.zz is fixed low. burst write a2+1 write a2 a1 a2 a4 clk cke# e# adv w# bwx# add dq g# write a1 nop burst write a2+3 write a2 write a3 nop burst write a4+1 stall burst write a4+2 burst write a4+3 a 3 d(a1) d(a2) d(a2+1) d(a2+3) d(a2) d(a3) d(a4) d(a4+1) don't care undefined t khkh t klkh t khkl t khckex t ckevkh t khex t evkh t khadvx t advvkh t khwx t wvkh t khbx t bvkh t khax t avkh t khdx t dvkh write a4 renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 14 / 25 m5m5v5636ug - 16 rev.2.0 (5)read/write timing note35.q(an) refers to output from address an. q(an+1) refers to output from the next internal burst address following an. note36. e# represents three signals. when e# is low, it represents e1# is low, e2 is high and e3# is low. note37.zz is fixed low. write a2 a1 a2 a5 q(a1) q(a3+1) q(a5) clk cke# e# adv w# bwx# add dq g# read a1 read a2 write a3 burst write a3+1 read a3 burst read a3+1 des elect write a4 stall read a5 burst read a5+1 burst read a5+2 a2 a3 a3 a4 d(a2) q(a2) d(a3) d(a3+1) q(a3) d(a4) don't care undefined t khkh t klkh t khkl t khckex t ckevkh t khex t evkh t khadvx t advvkh t khwx t wvkh t khbx t bvkh t khax t avkh t khqx1 t khqv t khq v t khdx t dvkh renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 15 / 25 m5m5v5636ug - 16 rev.2.0 (6)snooze mode timing clk zz all inputs (except zz) q deselect or read only snooze mode t zzs t zzrec renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 16 / 25 m5m5v5636ug - 16 rev.2.0 jtag port operation overview the jtag port on this sram operates in a ma nner consistent with ieee standard 1149.1 - 1990, a serial boundary scan interface standard (commonly referred to as jtag), but dose not implement all of the function required for 1149.1 compliance. the jtag port interfaces with conventional cmos logic level signaling. disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power - up and will remain inactive unless clocked. to assure normal operation of the sram with the jtag port unused, the tck, tdi a nd tms pins may be left floating or tied to high. the tdo pin should be left unconnected. jtag pin description test clock (tck) the tck input is clock for all tap events. all inputs are captured on the rising edge of tck and the test data out (tdo) prop agates from the falling edge of tck. test mode select (tms) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. test data in (tdi) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between the tdi and tdo pins. the register placed between the tdi and tdo pins is determined by the state of the tap controller st ate machine and the instruction that is currently loaded in the tap instruction resister (refer to the tap controller state diagram). an undriven tdi input will produce the same result as a logic one input level. test data out (tdo) the tdo output is acti ve depending on the state of the tap controller state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between the tdi and tdo pins. note: this device dose not have a trst (tap reset) p in. trst is optional in ieee 1149.1. the test - logic - reset state is entered while tms is held high for five rising edges of tck. the tap controller is also reset automatically at power - up. jtag port registers overview the various jtag registers, referred to as test access port or tap registers, are selected (one at a time) via the sequence of 1s and 0s applied to tms as tck is strobed. each of tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run - te st/idle, or the various data register states. instructions are 3 bits long. the instruction resister can be loaded when it is placed between the tdi and tdo pins. the instruction resister is automatically preloaded with the idcode instruction at power - up o r whenever the controller is placed in test - logic - reset state. renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 17 / 25 m5m5v5636ug - 16 rev.2.0 bypass register the bypass resister is a single - bit register that can be placed between the tdi and tdo pins. it allows serial test data to be passed through the sram's jtag port to another de vice in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the sram's input or i/o pins. the flip flops are then daisy chained tog ether so the levels found can be shifted serially out of the jtag port's tdo pins. the relationship between the device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the con trol of the tap controller, is loaded with the contents of the sram's i/o ring when the controller is in the capture - rd state and then is placed between the tdi and tdo pins when the controller is moved to the shift - dr state. sample - z, sample/preload and e xtest instruction can be used to activate the boundary scan register. identification (id) register the id register is a 32 - bit register that is loaded with a device and vender specific 32 - bit code when the controllers put in the capture - dr state with the idcode instruction loaded in the instruction register. the code is loaded from 32 - bit on - chip rom. it describes various attributes of the sram (see page 20). the register is then placed between the tdi and tdo pins when the controller is moved into shift - d r state. bit 0 in the register is the lsb and the first to reach the tdo pin when shifting begins. tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1 - 1990; standard (public) instructions, and dev ice specific (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap controller in this device is not fully 1194.1 - compliant because some of the mand atory 1149.1 instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads. this device will not perform intest or preload portion of the sample/preload command. when the tap controller is placed in the shift - ir state, the instruction register is placed between the tdi and tdo pins. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at the tdo output). for all instructions, the tap execute s newly loaded instructions only when the controller is moved to the update - ir state. the tap instruction set for this device is listed in the following table. instruction descriptions bypass when the bypass instruction is loaded in the instruction regis ter, the bypass register is placed between the tdi and tdo pins. this occurs when the tap controller is moved to the shift - dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/prel oad sample/preload is a standard1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller into the capture - dr state loads the data in the sram's input and i/o buffers into the boundary scan register. because the sram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. sram input signals must be stabilized for long enough to meet the tap's input data capture set - up plus hold time (tts plus tth). the sram's clock inputs need not b e paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to the shift - dr state then places the boundary scan register between the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the update - dr state with the sample/preload instruction loaded in the instruction register has the same effect as the pause - dr command. this functionality is not standard 1149.1 compliant . renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 18 / 25 m5m5v5636ug - 16 rev.2.0 extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all logic 0s. extest is not implemented in the tap controller, and therefore this device is not compliant to the 1149.1 s tandard. when the extest instruction is loaded into the instruction register, the device responds as if the sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest plac e the sram outputs in a high - z state. idcode the idcode instruction cause the id rom to be loaded into the id register when the controller is in the capture - dr state and places the id register between the tdi and tdo pins in the shift - dr state. the idcode instruction is the default instruction loaded in at power - up and any time the controller is placed in the test - logic - reset state. sample - z if the sample - z instruction is loaded in the instruction register, all sram outputs are forced to an inactive drive state (high - z) and the boundary scan register is placed between the tdi and tdo pins when the tap controller is moved to the shift - dr state. rfu these instructions are reserved for future use. do not use these instructions. jtag tap block diagram 31 30 29 . . . . . . 2 1 0 . . 2 1 0 0 . . . . . . . . . . . . . . . . 2 1 0 . . boundary scan register identification register instruction register bypass register tdo tdi test access port (tap) controller tms tck renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 19 / 25 m5m5v5636ug - 16 rev.2.0 boundary scan order bit bump pin name bit bump pin name bit bump pin name 0 8p a15 27 10a a8 54 1h mch 1 8r a16 28 10b a9 55 2h mch 2 9p a13 29 9a a17 56 2j dqd 3 9r a14 30 9b a18 57 1j dqd 4 10p a11 31 8a adv 58 2k dqd 5 10r a12 32 8b g# 59 1k dqd 6 11r a10 33 7a cke# 60 1l dqd 7 11n dqpa 34 7b w# 61 2l dqd 8 11m dqa 35 6b clk 62 1m dqd 9 10m dqa 36 6a e3# 63 2m dqd 10 10l dqa 37 5b bwa# 64 1n dqpd 11 11l dqa 38 5a bwb# 65 1r lbo# 12 10k dqa 39 4a bwc# 66 3r a4 13 11k dqa 40 4b bwd# 67 3p a5 14 10j dqa 41 3b e2 68 4r a2 15 11j dqa 42 3a e1# 69 4p a3 16 11h zz 43 2a a7 70 6p a1 17 7n mch 44 2b a6 71 6r a0 18 11g dqb 45 1c dqpc 19 10g dqb 46 1d dqc 20 11f dqb 47 2d dqc 21 10f dqb 48 1e dqc 22 11e dqb 49 2e dqc 23 10e dqb 50 1f dqc 24 11d dqb 51 2f dqc 25 10d dqb 52 1g dqc 26 11c dqpb 53 2g dqc renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 20 / 25 m5m5v5636ug - 16 rev.2.0 jtag tap controller state diagram tap controller dc electrical characteristics1 (ta=0 ~ 70 c, v dd =3.135 ~ 3.465v, u nless otherwise noted) limits symbol parameter condition min max unit v iht test port input high voltage 2.0 v ddq +0.3 ** v v ilt test port input low voltage - 0.3 ** 0.8 v v oht test port output high voltage i oh = - 100 a v ddq - 0.1 - v v olt test port ou tput low voltage i ol =+100 a - 0.1 v i int tms, tck and tdi input leakage current - 10 10 a i olt tdo output leakage current output disable, v out =0v ~ v ddq - 10 10 a note38. **input undershoot/overshoot voltage must be ? 1.0v renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 22 / 25 m5m5v5636ug - 16 rev.2.0 jtag tap instruction set summary instru ction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high - z state. this instruction is not 1149.1 - compliant. idcode 001 preloads id register and places it between tdi and tdo sample - z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all data output drivers to high - z rfu 011 do not use this instruction; reserved for future use. sample/preload 100 captures i/o ring conte nts. places the boundary scan register between tdi and tdo. this instruction dose not implement 1149.1 preload function and is therefore not 1149.1 - compliant. rfu 101 do not use this instruction; reserved for future use. rfu 110 do not use this instructi on; reserved for future use. bypass 111 places the bypass register between tdi and tdo. structure of identification register revision device information jedec vendor code of renesas bit no. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m5m5v5636 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 msb lsb renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 23 / 25 m5m5v5636ug - 16 rev.2.0 package outline 165(11x15) bump ball grid array(bga) pin pitch 1.00mm refer to jedec standard mo - 216, variati on cab - 1, which can be seen at: http://www.jedec.org/download/search/mo - 216c.pdf renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram 24 / 25 m5m5v5636ug - 16 rev.2.0 revision history rev. no. history date 1.0 the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. both renesas and mitsubishi jedec vendor code are as follows bit no. 11 10 9 8 7 6 5 4 3 2 1 renesas 0 1 0 0 0 1 0 0 0 1 1 mitsubishi 0 0 0 0 0 0 1 1 1 0 0 august 1, 2003 preliminary 2.0 eliminate preliminary be guaranteed 2.5v operation elim inate m5m5v5636ug - 13 changed pd( maximum power dissipation) from 1180mw to 1.6w march31, 2004 renesas lsis m5m5v5636ug ? 16 18874368 - bit(524288 - word by 36 - bit) network sram nippo n bldg.,6 - 2,oteamch i 2 - chome,chiyoda - ku,tokyo,100 - 000 4 japan renesas technology corporation puts the maximum effort into making semiconductor pr oducts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage.remember to give due consideration to safety when making your circuit de signs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customer s in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. renesas technology corporation assumes no responsibility for any damage, or infringement of any third - party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas te chnology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and produ cts. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein f or any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or i n part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destinat ion. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact renesas technology corporation for further details on these materials or the products contained t herein. rej03c0075 ? 2003 renesas technology corp. new publication, effective march 200 4 . s pecifications subject to change without notice. keep safety first in your circuit designs! notes regarding these materials |
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